An extremely efficient picture scaling processor is implemented in FPGA.
Keywords:
IQ (image quality), RCUs (reconfigurable calculation units), multiplier–adder (MA).Abstract
Many industries, including consumer electronics and medical imaging, use image scaling to enhance the
quality of images. Many real-time applications rely on scalability, which necessitates a low-cost VLSI solution. This
study offers a low-complexity, low-memory need, and high-quality VLSI implementation of an image scaling
processor. Using a clamp filter and bilinear interpolation, the proposed picture scaling method uses a sharpening
spatial filter. Prior to bilinear interpolation, spatial and clamp prefilters are utilised to reduce the blurriness and
aliasing effects. To preserve memory buffers and computing resources, we use a hybrid approach that combines a
spatial and a clamp filter. In order to save money on hardware, the reconfigurable unit utilises several adders. Filter
latency will be increased as a consequence. To decrease latency, we describe a high-speed parallel prefix-based link
adder. The results of the experiments will show that the proposed architecture is better in terms of space and power
overhead than earlier techniques to scaling pictures of lesser complexity.
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