VLSI Design Based Delay and Power Performance Comparison and Analysis of Multipliers

Authors

  • K.Bharatha Babu Anand Institute of Higher Technology Author
  • V.Anupriya Anand Institute of Higher Technology Author

Keywords:

— Vedic Multiplier, VLSI, Sutra, Power Performance

Abstract

Recently, the problem of power dissipation has become more important in VLSI design. The multiplier is a major drain on resources. The multiplier is a basic operation in arithmetic. This article examines a variety of multipliers at the algorithmic, circuit, and layout levels. The multiplier schematic was designed using TANNER TOOL. It has been possible to increase the speed and area of multipliers by utilising Vedic mathematics for multiplication. Vedic mathematics' "Ni khilam sutra" formula can multiply large numbers. One of the primary objectives is to increase speed while simultaneously decreasing power, area, and delay.

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Author Biographies

  • K.Bharatha Babu, Anand Institute of Higher Technology

    Department

  • V.Anupriya, Anand Institute of Higher Technology

    Department

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Published

2024-11-06

Issue

Section

Research Articles(s)