AN EFFICIENT STROBE SWITCH BASED CHIP-TO-CHIP INTERCONNECT FOR NNA’s
DOI:
https://doi.org/10.54228/mjaret07220013Keywords:
Chip-to-chip interconnection, deep neural network (DNN), hardware accelerator, interconnection architecture, network-on-chip (NoC).Abstract
Modern multi- or many-core devices may handle complicated data flows with energy efficiency by using network-on-chips (NoCs). A Neural Network Accelerators (NNA) is a linked collection of nodes called neurons that generally consists of many processing nodes. To manage the high neuron-to-neuron traffic, a multicore device might be used. Massive volumes of multicast-based traffic are sent on-chip or between chips, making the interconnection network design more difficult and posing a performance and energy barrier for NN systems. For virtual-channel routing, the proposed system combines scoring crossbar arbitration, arbitration interception, and route calculation parallelization approaches, resulting in a high-throughput NoC with less expensive hardware for multicast-based traffic. Every time this system connects and disconnects, it will automatically self-repair the connection and give a workable connection route. Additionally, the network configuration will often alter depending on the cost value. With that route controller and switch assigned, a strobe cross bar switch is implemented for improved speed and performance. The power, area, logical, and speed of the proposed architecture are contrasted with those of the current design.
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