Design of Parity preserving BCD adder using Reversible Gate Logic

Authors

  • Mrs.K. Lakshmi Anand Institute of Higher Technology Author

Keywords:

BCD Adder, Reversible Logic, Double Feynman Gate, Islamic Gate (IG).

Abstract

Nanotechnology, optical computing, quantum computing, and lw-power CMOS architecture are all using
reversible logic circuits. In binary-based electronics, low-power and high-speed adder cells (such as the BCD adder)
are employed. Binary addition is a basic operation in almost all digital circuits. All other arithmetic operations may
be synthesized from it. The major problem now is to reduce the power consumption of adder circuits while retaining
excellent performance across a variety of circuit configurations. For error detection in digital systems, parity
preservation is also an option. BCD adder design that is fault resistant and preserves parity is suggested in this paper.
Reversible logic gates such as IG, FRG, and F2G are used in the suggested technique to reduce the circuit's power
consumption and quantum cost. It is compared to the present circuit in terms of the number of constant inputs and
garbage outputs, the latency, and the quantum cost.

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Author Biography

  • Mrs.K. Lakshmi, Anand Institute of Higher Technology

    Assistant Professor, Department of Electronics and Communication Engineering

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Published

2021-12-30

Issue

Vol. 1 No. 5 (2021)

Section

Research Articles(s)

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